Reconvergent Fanout Removal Through Partial BIST Insertion
نویسنده
چکیده
The chief goal of partial scan/BIST selection is to identify the minimum number of flip flops in a design which can be converted into test flip flops to enable high fault coverage. We propose the elimination of reconvergent fanout during partial scan/BIST selection by choosing flip flops on reconvergent fanout paths. We present a partial scan/BIST selection algorithm which minimizes reconvergent fanout. Experimental results show the significant fault coverage gain enabled by this approach.
منابع مشابه
Partial BIST Insertion to Eliminate Data Correlation
A new partial BIST insertion approach based on eliminating data correlation to improve pseudo-random testability is presented. Data correlation causes the circuit to be in a subset of the states more or less frequently, which leads to low fault coverage in pseudo-random test. One important cause of correlation is reconvergent fanout. Incorporating BIST test flip-flops into reconvergent paths wi...
متن کاملMore Accurate Polynomial-Time Min-Max Timing Simulation
We describe a polynomial-time algorithm for min-max timing simulation of combinational circuits. Our algorithm reports conservative bounds on the propagationdelays from each primary input to each gate, for use in the timing verification of fundamental-mode asynchronous circuits. A new reconvergent fanout analysis technique is presented. Our algorithm produces more accurate results than previous...
متن کاملMin-Max Timing Analysis and An Application to Asynchronous Circuits
Modern high-performance asynchronous circuits depend on timing constraints for correct operation, so timing analyzers are essential asynchronous design tools. In this paper, we present a 13-valued abstract waveform algebra and a polynomial-time min-max timing simulation algorithm for use in efficient, approximate timing analysis of asynchronous circuits with bounded component delays. Unlike sev...
متن کاملLearning Techniques for Automatic Test Pattern Generation using Boolean Satisfiability
Automatic Test Pattern Generation (ATPG) is one of the core problems in testing of digital circuits. ATPG algorithms based on Boolean Satisfiability (SAT) turned out to be very powerful, due to great advances in the performance of satisfiability solvers for propositional logic in the last two decades. SAT-based ATPG clearly outperforms classical approaches especially for hard-to-detect faults. ...
متن کاملOn Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs
This paper presents the integration of a proprietary hierarchical and distributed test access mechanism called HDBIST and a BIST insertion commercial tool. The paper briefly describes the architecture and the features of both the environments and it presents some experimental results obtained on an industrial SoC. 1. The HDBIST architecture HDBIST (Hierarchical-Distributed-Data BIST) is a propr...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2000